今天上機考試 經過一番苦戰 終於過啦~~~~
超開心:>module top;
wire a, A, b, B, c, C, d, D, F, F1, F2, F3, F4, F5;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);
nand S1(a, A, A);
nand S2(b, B, B);
nand S3(c, C, C);
nand S4(d, D, D);
nand C5(F5, a ,b , C);
nand C1(F2, A ,B , d);
nand C2(F4, a, C, d);
nand C3(F3, A, B, C);
nand C4(F1, A, b, c, D);
nand o1(F, F5, F4, F2, F3, F1);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(PERIOD/2) clk=~clk;
end
always@(posedge clk)
if($time>1000)$stop;
endmodule
